The present invention relates to a DC/DC converter, and, more particularly, to a synchronous rectification-type DC/DC converter used as a power supply for a variety of electronic devices and a control circuit for the converter.
As shown in FIG. 1, a conventional synchronous rectification-type DC/DC converter 1 comprises a control circuit 2 formed on a single semiconductor integrated circuit substrate and seven elements 3 to 9 mounted externally.
A first drive signal SG1 of the control circuit 2 is supplied to the gate of the main switching element 3, which is an enhancement-type N-channel MOS transistor. The switching element 3 operates as a main switch for driving a load. The drain of the switching element 3 is supplied with a supply voltage Ve from a battery, while the source of the switching element 3 is connected to the drain of the synchronous switching element 4, which is an enhancement-type N-channel MOS transistor. The gate of the synchronous switching element 4 is supplied with a second drive signal SG2 of the control circuit 2, while the source thereof is connected to the ground GND.
A node between the main switching element 3 and the synchronous switching element 4 is connected via a choke coil 5 to an output terminal To of the DC/DC converter 1 and also through the fly-back diode 6 to the ground GND. The synchronous switching element 4 operates when the DC/DC converter 1 is flying back, thus reducing loss at the fly-back diode 6.
The output terminal To is connected via the smoothing capacitor 7 to the ground GND. The output terminal To, which outputs voltage Vo of the DC/DC converter 1, is connected to the load of a control unit such as a CPU (not shown). The choke coil 5 and the smoothing capacitor 7 constitute a smoothing circuit. The output voltage Vo is divided by the resistors 8 and 9, and a divided voltage V2 is fed back to the control circuit 2.
The control circuit 2 includes an error amplification circuit 11, a PWM comparison circuit 12, a triangular wave oscillation circuit 13, an idle period setting circuit 14, and first and second output circuits 15 and 16.
The error amplification circuit 11 compares the divided voltage V2 supplied to an inverting input terminal and a reference voltage Vr (set voltage) supplied to a non-inverting input terminal from a reference power supply E1 and amplifies a differential voltage between the two, thus generating an error signal S1.
The PWM comparison circuit 12 compares the error signal S1 supplied to the non-inverting input terminal from the error amplification circuit 11 and a triangular wave signal S2 supplied to the inverting input terminal from the triangular wave oscillation circuit 13, to generate a pulse signal S3 having a low (L) level in a period for which the triangular wave signal S2 is higher in level than the error signal S1 and the pulse signal S3 having a high (H) level in a period opposite to it.
Based on the pulse signal S3 supplied from the PWM comparison circuit 12, the idle period setting circuit 14 generates first and second control signals S4 and S5 such that the main switching element 3 and the synchronous switching element 4 are turned ON and OFF substantially complementarily and also such that they are not turned ON simultaneously (that is, the switching elements 3 and 4 are turned ON and OFF alternately at different timings). A period in which the switching elements 3 and 4 are turned OFF simultaneously is referred to as a synchronous rectification idle period (hereinafter called idle period). The idle period is set to prevent the system from being destroyed by an excessive current which would flow through the switching elements 3 and 4 if the main switching elements 3 and 4 were turned ON simultaneously.
The first output circuit 15 amplifies the first control signal S4 supplied from the idle period setting circuit 14, to generate a first drive signal SG1 supplied to the main switching element 3. The second output circuit 16 amplifies the second control signal S5 supplied from the idle period setting circuit 14, to generate a second drive signal SG2 supplied to the synchronous switching element 4.
As shown in FIG. 2, the idle period setting circuit 14 includes five inverter circuits 21 to 25, two transistors T1 and T2, two power supplies 26 and 27, and two capacitors C1 and C2.
The pulse signal S3 is supplied to the inverter circuit 21, which in turn supplies an inverted signal of the pulse signal S3 to the gate of the N-channel MOS transistor T1. The source of the transistor T1 is connected to the ground GND and the drain thereof is connected to the current source 26. A node between the transistor T1 and the current source 26 is connected via the inverter circuit 22 to the inverter circuit 23, which outputs the first control signal S4, and also to the ground GND via the capacitor C1.
As shown in FIG. 3, when the pulse signal S3 rises, an input signal S6 of the inverter circuit 22 also rises in accordance with a current 11 from the current source 26 and a capacitance of the capacitor C1. Subsequently, when the pulse signal S3 falls, the transistor T1 is turned ON, thus causing the input signal S6 to fall rapidly. When the voltage of the input signal S6 exceeds a threshold voltage Vth of the inverter circuit 22, the inverter circuit 22 inverts the input signal S6. Therefore, the first control signal S4 rises as delayed with respect to the rising timing of the pulse signal S3 by time td1 which corresponds to charging time of the capacitor C1 and falls substantially at the same time as the pulse signal S3 falls. The delay time td1 is obtained by:td1=Vth*C1/I1
The pulse signal S3 is supplied to the gate of the N-channel MOS transistor T2. The source of the transistor T1 is connected to the ground GND and the drain thereof is connected to the current source 27. A node between the transistor T2 and the current source 27 is connected via the inverter circuit 24 to the inverter circuit 25, which outputs the second control signal S5, and also to the ground GND via the capacitor C2.
As shown in FIG. 3, when the pulse signal S3 rises, the transistor T2 is turned ON, thus causing an input signal S7 of the inverter circuit 24 to fall rapidly. Subsequently, when the pulse signal S3 rises, the input signal S7 rises in accordance with a current I2 from the current source 27 and a capacitance of the capacitor C2. When the voltage of the input signal S7 exceeds a threshold voltage Vth of the inverter circuit 24, the inverter circuit 24 inverts the input signal S7. Therefore, the second control signal S5 falls substantially at the same time as the pulse signal S3 rises and rises as delayed with respect to the rising timing of the pulse signal S3 by delay time td2 which corresponds to charging time of the capacitor C2. The delay time td2 is obtained by:td2=Vth*C2/I2
Preferably the DC/DC converter 1 operates on a low supply voltage in order to reduce power consumption. The idle period setting circuit 14, however, generates the first control signal S4 which has a pulse width smaller than that of the pulse signal S3 by the delay time td1. Accordingly, as shown in FIG. 4, an ON-duty ratio of the first control signal S4 with respect to the voltage of the error signal S1 becomes smaller than that of ideal characteristics. Therefore, it is impossible to set the duty ratio of the first control signal S4 (i.e., the first drive signal SG1) to a high value (for example, a value in the vicinity of 100%). For this reason, in the conventional DC/DC converter 1, it is difficult to lower the supply voltage to reduce the power consumption.